The present application relates generally to semiconductor devices, and more specifically to methods for manufacturing fin field effect transistors.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
The gate structure may be formed using a gate-first or a gate-last fabrication process. A gate-last process, such as a replacement metal gate (RMG) process, utilizes a sacrificial or dummy gate, which is typically replaced by a functional gate after device activation, i.e., after dopant implantation into source/drain regions of the fins and an associated drive-in anneal, in order to avoid exposing the functional gate materials to the thermal budget associated with activation.
Prior to removing the sacrificial gate and forming a functional gate structure, a gate cut module may be used to sever the sacrificial gate layer and form an opening within select regions of the device architecture in order to isolate adjacent devices. In association with such a process, the sacrificial gate layer material removed from the openings is replaced with another dielectric material. However, in advanced nodes, the proximity of the backfilled layer to an adjacent fin may result in insufficient space for deposition of a complete functional gate structure (e.g., gate dielectric and gate conductor layers).